1. Field of the Invention
The present invention relates to a circuit for performing an auto-verifying program on a non-volatile memory cell of a semiconductor memory device, and in particular to a circuit for performing an auto-verifying program on a non-volatile memory cell which can be sensed with an auto-verifying program for comparing currents, and which can limit a maximum value of a cell current.
2. Description of the Background Art
As known methods of programming an EEPROM flash memory device among non-volatile memories, there have been employed a method of sequentially programming and verifying the memory, and an auto-verifying programming method or a simultaneous programming and verifying method which applies a long program pulse until the memory is completely programmed, and removes all program states once it is programmed.
In the auto-verifying programming method, whether a memory cell is programmed to a wanted extent is generally determined by observing a current variation of the memory cell.
FIG. 1 is a schematic circuit diagram illustrating a conventional auto-verifying programming device. Referring to FIG. 1, the auto-verifying programming device includes a load unit 1 connected to a selected cell FMC and serving as a load, a voltage clamping unit 2 applying a clamp voltage VCLAMP to a drain of the selected cell FMC, and a comparison unit 3 comparing a voltage of a first node ND1 with a reference voltage VREF, and outputting a program enable signal PROEN.
The load unit 1 includes a PMOS diode formed by a PMOS transistor PMD having its source connected to receive the programming voltage VPP, and its gate and drain commonly-connected, that is, being diode-connected to the drain of the selected cell FMC.
The voltage clamping unit 2 includes: a first PMOS transistor PM1 and a second PMOS transistor PM2 in parallel and having their respective sources connected to receive the programming voltage VPP, and their gates commonly connected, the gate and drain of the second PMOS transistor PM2 being commonly connected; a first NMOS transistor NM1 having its gate connected to the drain of the selected cell FMC and its drain connected to the drain of the first PMOS transistor PM1; a second NMOS transistor NM2 having its gate connected to receive the clamp voltage VCLAMP, and its drain connected to the drain of the second PMOS transistor PM2; a third NMOS transistor NM3 having its gate connected to receive a clamping control signal CLAMPEN, its drain connected to the commonly-connected sources of the first and second NMOS transistors NM1, NM2, and its source connected to a ground voltage VSS; and a fourth NMOS transistor NM4 having its gate connected to the commonly-connected drains of the first PMOS transistor PM1 and the first NMOS transistor NM1, its drain connected to the first node ND1, and its source connected to the drain of the selected cell FMC.
The comparison unit 3 is a differential amplifier having its first input terminal connected to receive a voltage of the first node ND1, and its second input terminal connected to receive the reference voltage VREF.
The operation of the thusly-constituted circuit for performing the auto-verifying program on the EEPROM flash memory will now be described.
First, when the selected cell FMC is programmed, as shown in FIG. 2, a voltage variation of the first node ND1 which is varied at a high potential according to a load generated by the diode-connected PMOS transistor PMD is compared with the reference voltage VREF by the differential amplifier composing the comparison unit 3.
Here, at a point that the voltage of the first node ND1 becomes higher than the reference voltage VREF, namely at a point (A) indicated in FIG. 2, the comparison unit 3 outputs the program enable signal PROEN. The program enable signal PROEN is outputted as the clamping control signal CLAMPEN by a logic circuit (not shown), and applied to the gate of the third NMOS transistor NM3 in the voltage clamping unit 2.
Thereupon, the voltage clamping unit 2 ceases to apply the clamp voltage VCLAMP to the selected cell FMC.
This operation implies that the programming of the selected cell FMC is completed.
The general circuit for performing the auto-verifying programming on the memory cell compares the currents of the memory cell by employing a voltage comparator, and employs a mapping for the current and voltage. It is thus difficult to directly compare the currents.
In addition, the amount of current flowing while the memory cell is programmed is a factor determining the number of the memory cells which are programmable at a time. As the current increases, it imposes a burden on the other circuits in the memory chip, such as a high voltage supply unit and a sense amplifier.
FIG. 3 is a circuit diagram illustrating a conventional circuit for performing an auto-verifying program on an EEPROM flash memory. Referring to FIG. 3, the circuit includes: a first current supply unit 10 supplying a reference current IREF to the selected cell FMC; a second current supply unit 20 supplying an additional current IADD to the selected cell, and a logic circuit unit 30 isolating the first current supply unit 10 and the second current supply unit 20 from the selected cell FMC when the program is completed.
The first current supply unit 10 includes: a first PMOS transistor PM11 and a second PMOS transistor PM12 having their respective sources connected to receive the programming voltage VPP, and their gates commonly connected, the drain of the first PMOS transistor PM11 being connected to the drain of the selected cell FMC, the gate and drain of the second PMOS transistor PM12 being commonly connected; a first NMOS transistor NM11 having its drain connected to the drain of the second PMOS transistor PM12, its gate and drain commonly connected, and its source connected to the ground voltage VSS.
The second current supply unit 20 includes an NMOS transistor NM21 having its drain connected to receive the programming voltage VPP, its source connected to the drain of the selected cell FMC, and its gate connected to receive the clamping control signal CLAMPEN from the logic circuit unit 30.
The logic circuit unit 30 is connected in series between the programming voltage VPP and the ground voltage VSS, and includes: a PMOS transistor PM31 having its gate connected to the drain of the selected cell FMC, and an NMOS transistor NM31 having its gate connected to the gate of the NMOS transistor NM11 in the first current supply unit 10. The commonly-connected drains of the PMOS transistor PM31 and the NMOS transistor NM31 are connected to the gate of the NMOS transistor NM21 of the second current supply unit 20.
The operation of the thusly-constituted circuit for performing the auto-verifying program on the EEPROM flash memory will now be explained.
The first current supply unit 10 supplies the reference current IREF to the selected cell FMC, and the second current supply unit 20 supplies the additional current IADD to the selected cell FMC, thereby proceeding with the auto-verifying program.
Referring to FIG. 4, at a point (B) that the cell current ICELL becomes identical to the reference current IREF, the voltage at the drain of the selected cell FMC becomes a low potential, and is sharply changed to a high potential. Accordingly, the NMOS transistor NM21 of the second current supply unit 20 is turned off the by CLAMPEN signal from the logic circuit unit 30, thereby completing the program.
As described above, the conventional circuit for performing the auto-verifying program on the EEPROM flash memory serves to detect a programming point by comparing the point where the reference current IREF becomes identical to the cell current ICELL, without requiring a special comparator.
However, the conventional circuit for performing the auto-verifying program on the EEPROM flash memory has a disadvantage in that it cannot limit a maximum value of the cell current, and thus applies stress to the circuit, which results in large current consumption.